Method of verifying designed circuits

ABSTRACT

Disclosed is a designed-circuit-verifying method for verifying an LSI or a wiring-substrate circuit with ease at the design stage of the circuit. An analysis based on simulation of a circuit allows electrical characteristics of a designed circuit to be detected at a design stage and compared with reference data. In accordance with a result of the comparison, an item to be corrected, the location of the item and other information on the item can be identified. In addition, since details of the correction can be displayed at an identified position on the designed circuit, the design of the circuit can be corrected. Thus, the design efficiency of the circuit can be improved.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an LSI and a wiring-substratecircuit. More particularly, the present invention relates to a methodused for verifying a designed circuit in order to detect and correctelectrical characteristics of circuit components composing the designedcircuit.

[0002] As has been commonly known, there are voltage drops referred toas the so-called IR drops inside an LSI or a wiring-substrate circuitfrom a level of a voltage appearing at a power-supply pin of the LSI orthe wiring-substrate circuit due to an effect of an operation currentflowing during an operation of the LSI or the wiring-substrate circuit.

[0003] There has been proposed a variety of techniques for analyzing aphenomenon of a drop in power-supply voltage. In accordance with thetechniques, however, a result of analysis is revealed by merelydisplaying the magnitude of a voltage drop along a wire, at a via holeor a cell terminal or merely displaying a current density. There has notbeen reported a technique whereby a result of analysis identifies thelocation of a wire abnormality so as to allow the abnormality to becorrected with ease.

SUMMARY OF THE INVENTION

[0004] It is thus an object of the present invention addressing theproblems described above to provide a designed-circuit-verifying methodfor verifying a designed circuit with ease at a designed stage of thecircuit or an LSI containing the circuit.

[0005] To solve the problems described above, according to a firstaspect of the present invention, there is provided adesigned-circuit-verifying method including: a process of designing apredetermined circuit; a process of simulating reference datarepresenting electrical characteristics of circuit components composingthe designed circuit; and a process of detecting electricalcharacteristics of the circuit components and comparing the detectedelectrical characteristics with the reference data.

[0006] The designed-circuit-verifying method is also referred tohereafter as an invention verification method.

[0007] In accordance with the invention verification method, for acircuit component of a designed circuit, electrical characteristics ofthe circuit component are detected by simulation and compared withreference data. Thus, an electrical characteristic different from thereference data or the location of a circuit component having such anelectrical characteristic can be identified with ease. On the basis of aresult of comparison, it is possible to show an electricalcharacteristic different from the reference data on a display of acircuit component exhibiting the electrical characteristic. By showingsuch an electrical characteristic on a display of the circuit component,the designed circuit can be corrected with ease. As a result, it ispossible to provide a method of verifying a designed circuit to increasea design efficiency.

[0008] It is desirable to provide an invention verification method forcomparing an electrical characteristic of each circuit componentemployed in a designed circuit with reference data and identifying anelectrical component to be corrected on the basis of a result ofcomparison so as to allow the designed circuit to be corrected withease.

[0009] It is thus desirable to further provide the inventionverification method with: a process of displaying reference datarepresenting an electrical characteristic of a circuit componentemployed in a designed circuit on a computer screen if necessary; aprocess of fetching detected data of the electrical characteristic ofthe circuit component; a process of comparing the fetched electricalcharacteristic with the reference data and forming a judgment on aresult of comparison; and a process of displaying a result of thejudgment on the computer screen.

[0010] In this case, it is desirable to select at least one electricalcharacteristic to be detected among a group of electricalcharacteristics including a voltage applied to a power-supply wire, avoltage drop, a power consumption, a current and a current direction,which are observable for each circuit component employed in the designedcircuit.

[0011] To put it in detail, after simulation of voltage drops and otherson the computer screen is ended, on the basis of comparison of ananalysis result with reference data and on the basis of a judgment on aresult of the comparison, detected data is fetched. For example, inaddition to displays of a voltage drop along a Vdd wire, a voltage dropat a via hole, a ground bounce on a Vss wire and a ground bounce at avia hole, voltages supplied to a cell and a macro or an LSI are alsodisplayed. In the case of a cell to which voltages Vdd and Vss aresupplied, for example, a difference in electrical potential between thevoltages vdd and Vss is displayed. As an alternative, a sum of a voltagedrop of the voltage Vdd and a ground bounce of the voltage Vss isdisplayed. The displays are graphical displays, which are colored inaccordance with their values, or ASCII outputs sorted in an order ofascending/descending values.

[0012] As another example, the direction of a current flowing through awire is displayed so as to allow the design engineer to verify that thecurrent indeed flows in a direction intended by the engineer. Inaddition, in case a current flows in a direction opposite to thesupposed direction, that is, in case a current flows out from a terminalof a macro or a cell instead of flowing into the terminal as expected,or flows into a terminal of a macro or a cell instead of flowing outfrom the terminal as expected, the display also includes a warningidentifying the terminal.

[0013] As a further example, a power consumption (or a current) per unitarea of a cell or a macro is computed and displayed in a color dependingon the value of the power consumption (or the current) or output at alocation among those arranged in an ASCII sort. A power consumption (ora current) per unit area of a cell or a macro is defined as a ratio of apower consumption (or a current) of the cell or the macro to the area ofthe cell or the macro.

[0014] It is desirable to select at least one electrical characteristicto be detected among a group of electrical characteristics including acurrent or the density of a current flowing through each connection holeof every circuit component, a current or the density of a currentflowing through each wire, a current or the density of a current flowingthrough a multi-layer wiring substrate, a supplied voltage, a voltagedrop and the location of each connection hole.

[0015] As a still further example, the display includes a warningidentifying a via hole, a contact or a wire, through which almost nocurrent is flowing, or a current smaller than a specified magnitude or acurrent having a density smaller than specified value is flowing. Suchvia holes, contacts and wires are displayed in a sorted order oftypically ascending values. Portions of wires having electric potentialsdifferent from each other may be located at positions of the same planarcoordinates but pertain to different layers. In case a difference inpower-supply voltage drop between such wire portions is greater than aspecified value, the coordinates of the positions of the wire portionsare identified and a warning for creation of a via hole is issued.

[0016] The user is also allowed to determine whether or not to displaysuch information in dependence on typically a distance between layers orthe number of layers. In addition, if a signal line is sandwichedbetween 2 power-supply-wiring layers in a multi-layer structure, theuser is allowed to select an option of displaying no warning.

[0017] The above and the other objects, features and advantages of thepresent invention will be apparent from the following detaileddescription of the preferred embodiment of the invention in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a schematic diagram showing typical drops in suppliedvoltage in accordance with an embodiment of the present invention;

[0019]FIG. 2 is a diagram showing typical displays according to the sameembodiment;

[0020]FIGS. 3A and 3B are diagrams showing typical displays according tothe same embodiment;

[0021]FIG. 4 is a diagram showing typical displays according to the sameembodiment;

[0022]FIG. 5 is a diagram showing typical displays according to the sameembodiment;

[0023]FIG. 6 is a diagram showing typical displays according to the sameembodiment; and

[0024]FIG. 7 is a diagram showing typical displays according to the sameembodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0025] An embodiment of the present invention is explained concretely byreferring to diagrams.

[0026] There is a variety of methods of voltage-drop simulation. Inaccordance with a typical method of voltage-drop simulation, the powerconsumption of each cell is found by logic simulation, and the parasiticresistance as well the stray capacitance of a power-supply wire arecomputed from layout data. The power consumption, the parasiticresistance and the stray capacitance are combined to create a net list,and a voltage drop along the wire as well as a voltage drop at the cellare finally found.

[0027] In addition, there has been reported a number of programs fordisplaying results by outputting voltage drops and current densities asASCII data or as computer graphics with colors varying in dependence onthe values of the results.

[0028] In this embodiment, however, simulation of typically a voltagedrop along a power-supply wire of an LSI is carried out as describedabove. After the simulation is ended, data based on results of analysisis displayed as described below to improve the design efficiency.

[0029]FIG. 1 is a diagram showing drops in voltages supplied to a cell.To be more specific, the figure shows a voltage drop occurring on apower-supply-side wire 2 a relative to a ground-side wire 2 b inpower-supply system 1 for a cell 1 and a voltage drop occurring on apower-supply-side wire 3 a relative to a ground-side wire 3 b inpower-supply system 2 for the same cell.

[0030] To put it in detail, voltage drops of powers supplied toterminals of a cell or an LSI are input to a computer screen and alargest value among the voltage drops on the power-supply side is foundfor each power-supply system. By the same token, ground bounces of thepowers are input to the computer screen and a largest value among theground bounces on the ground side is found for each power-supply system.Then, a sum of the largest value among the voltage drops on thepower-supply side and the largest value among the ground bounces on theground side is found for each of the power-supply systems. Each of thesums is displayed as a voltage drop of a power supplied to the cell orthe LSI.

[0031] For example, power-supply systems are connected to the cell 1 assystems 1 and 2 as shown in FIG. 1. The cell 1 has terminals Vdd1 andVdd2 connected to system 1 by the power-supply-side wire 2 a andterminals Vss1 and Vss2 connected to system 1 by the ground-side wire 2b. By the same token, the cell 1 is also provided with terminals Avd1and Avd2 connected to system 2 by the power-supply-side wire 3 a andterminals Avs1 and Avs2 connected to system 2 by the ground-side wire 3b. Systems 1 and 2 each apply a voltage of 1.5 V to the cell 1. Thepower-supply voltage drops at the power-supply-side terminals and theground bounces at the ground-side terminals are Vdd1=0.1 V, Vdd2=0.2 V,Vss1=0.1 V, Vss2=0.05 V, Avd1=0.15 V, Avd2=0.1 V, Avs1=0.15 V andAvs2=0.2 V.

[0032] First of all, a largest value among the voltage drops at theterminals Vdd and Vdd2 of power-supply system 1 is found. In thisexample, the largest value is the voltage drop Vdd2 of 0.2 V. Then, alargest value among the ground bounces at the terminals Vss1 and Vss2 ofpower-supply system 1 is found. In this example, the largest value isthe ground bounce Vss1 of 0.1 V. Thus, the voltage drop of a powersupplied by power-supply system 1 is found to be 0.3 V which is the sumof the voltage drop Vdd2 and the ground bounce Vss1. By the same token,the voltage drop of a power supplied by powersupply system 2 is found tobe 0.35 V which is the sum of the voltage drop Avd1 and the groundbounce Avs2.

[0033] Then, these pieces of information are displayed as drops inpower-supply voltage for the cell 1. The display includes the name ofthe cell 1 as well as the names of power-supply systems 1 and 2 alongwith their drops in power-supply voltage. In place of the drops inpower-supply voltage, the display may include net voltages applied bythe power-supply systems to the cell 1. The net voltages are obtained bysubtracting the drops in power-supply voltage from the original voltagesgenerated by the power-supply systems 1 and 2.

[0034]FIG. 2 is a typical display showing the drops in power-supplyvoltage, which are included in the display shown in FIG. 1.

[0035] To be more specific, typical display 1 in FIG. 2 shows the nameof a cell as well as numerical values of voltage drops for power-supplysystems 1 and 2.

[0036] Typical display 2 in FIG. 2 shows the name of a cell as well asnumerical values of net voltages actually supplied by power-supplysystems 1 and 2.

[0037] Typical display 3 in FIG. 2 shows cells or macros A1 to A6colored differently in accordance with the values of voltage drops ornet voltages actually applied by power supply systems in a display area4A. The meanings of colors applied to the cells or macros Al to A6 needto be determined in advance.

[0038]FIGS. 3A and 3B are diagrams each showing directions of currentsflowing to macros in a designed circuit.

[0039] To be more specific, FIG. 3A shows a layout of macros 6 a to 6 das well as wires 5 and 7 in a display area 4B. FIG. 3B is a diagramshowing an enlarged partial area E of the layout as well as thedirection of a current flowing through the wire 5 and the direction of acurrent flowing from the wire 5 to the macro 6 d through the wire 7. Thedirections of the currents are each explicitly represented by arrowsallowing the directions to be verified with ease.

[0040]FIG. 4 is a typical diagram showing a location detected by ananalysis based on simulation as a location at which a current is flowingin a direction opposite to the supposed direction.

[0041] That is to say, normally, currents flow into a cell or a macrothrough power-supply-system terminals 8 a to 8 c and flow out from thecell or the macro through ground-system terminals 9 a to 9 c as shown intypical display 2. As shown in the same figure, however, a current flowsthrough the ground-system terminal 9 b in a direction opposite to thesupposed direction and a warning indicates the location of a wireconnected to the terminal 9 b.

[0042] To be more specific, typical display 1 in FIG. 4 showscoordinates of the location at which a current is flowing in a directionopposite to the supposed direction. The display shows coordinatesX1=1,000 and Y1=500. Typical display 2 in FIG. 4 shows a typicalgraphical display. As shown in the figure, the ground-system terminal 9b and the wire connected to the terminal 9 b are displayed in a colordifferent from the rest. The figure also shows a warning displayindicating the location of the wire connected to the ground-systemterminal 9 b.

[0043]FIG. 5 is a diagram showing power consumptions.

[0044] A power consumption (or a current) per unit area is computed fora region occupied by a cell or a macro. That is to say, a power or acurrent consumed by a cell or a macro is divided by the area of a regionoccupied by the cell of the macro, being converted into a powerconsumption (or a current) per unit area. Power consumptions (orcurrents) per unit area are then sorted into an ascending or descendingorder. As an alternative, the power consumptions (or the currents) perunit area are displayed in as graphical representations with colorsvarying in dependence on the values of the power consumptions (or thecurrents) per unit area.

[0045] For example, in typical display 1 shown in FIG. 5, names of cellsand power consumptions (or currents) per unit area for the cells aredisplayed in an ASCII format, being arranged in an order of descendingvalues of the power consumptions (or the currents) per unit area.

[0046] As another example, in typical display 2 appearing in a displayarea 4C as shown in typical display 2 in FIG. 5, power consumptions (orcurrents) per unit area for cells and macros B1 to B6 are displayed asgraphical representations with colors varying in dependence on thevalues of the power consumptions (or the currents) per unit area. Alsoin this case, the meanings of the colors applied to the cells or macrosB1 to B6 need to be determined in advance.

[0047]FIG. 6 is a diagram showing typical displays of locations ofinactive wires detected as a result of an analysis based on simulation.

[0048] A result of an analysis outputs a warning identifying coordinatesof a wire or a via hole, through which almost no current flows or awarning identifying coordinates of a wire or a via hole, through whichonly a current with a magnitude or a density smaller than a valuespecified by the user flows. Such locations can each be displayed asASCII data or as graphical representations with colors varying independence on the magnitudes of the currents.

[0049] For example, in typical display 1 shown in FIG. 6, warnings areeach displayed to indicate coordinates X1 and Y1 of a wire or a viahole, through which only a current with a small magnitude or a smalldensity flows.

[0050] As another example, in typical display 2 shown in FIG. 6, a viahole 12 connecting an A wire 10 on a layer to a B wire 11 on anotherlayer and a C wire 13 are each pointed out as an inactive location in amulti-layer structure. As shown in the figure, the via hole 12 and the Cwire 13 are each displayed in a color different from the rest.

[0051]FIG. 7 is a diagram showing typical displays showing warningssuggesting addition of via holes at particular locations detected as aresult of an analysis based on simulation.

[0052] Power-supply wires of different layers in a multi-layer structuremay be laid out to pass through respective layer points having the sameplanar coordinates. If the points on the different layers are notconnected to each other by a via hole and the difference in voltage dropbetween the two points is at least equal to a predetermined value, awarning is displayed to indicate the common planar coordinates of thepoints. The predetermined value can be a default value or a valuespecified by the user.

[0053] For example, in typical display 1 shown in FIG. 7, warnings areeach displayed to indicate planar coordinates X1 and Y1 of a locationwith no via hole and a difference in voltage drop at the location.

[0054] As another example, in typical display 2 shown in FIG. 7, awarning is shown to indicate a location at which a via hole 14 is to beadded to connect an A wire 10 on a layer to a B wire 11 on another layerin a multi-layer structure.

[0055] To put it in detail, the A wire 10 on a layer crosses the B wire11 on another layer at a location as shown in FIG. 7. At the location,however, the via hole 14 does not exist and, in addition, a differencein voltage drop at the location is at least equal to a predeterminedvalue. In this case, a warning is displayed to point out the location.In dependence on the distance between two adjacent layers or the numberof layers, however, such a warning may or may not be displayed.

[0056] In accordance with this embodiment, a designed circuit ofpower-supply wires used in an LSI is analyzed by simulation wherebyelectrical characteristics are compared with their respective pieces ofreference data to detect an electrical characteristic different from itsreference data, and the location of such an electrical characteristic isdisplayed on the basis of a result of detection. It is thus possible toprovide remarkable effects 1 to 6 described as follows:

[0057] 1: It is possible to easily form a judgment as to whether or notan expected voltage is supplied to each device portion of an LSI or awiring-substrate circuit.

[0058] 2: It is possible to verify whether a current is flowing in anexpected direction and whether a micro bypasses a current to anotherportion as well as to easily determine a location to which apower-supply pad is to be added.

[0059] 3: A direction is given to point out a location at which anunexpected current is flowing.

[0060] 4: It is possible to intuitively determine which portion consumesa large current, and a direction is given to provide an optimumpower-supply wire.

[0061] 5: The method provided by the present invention is useful fordeletion of an all but ineffective wire. In addition, an unconnectedwire or an uncreated via hole due to incorrect wiring can be detectedwith ease.

[0062] 6: A forgotten process to bore a via hole can be verified. Suchverification serves as a direction for correcting the effect of avoltage. In addition, by displaying specified values in a graduallydescending order starting with a value large to a certain extent, it ispossible to classify the display by candidates for a location throughwhich a via hole is to be bored and by their levels of priority.

[0063] It is possible to make a variety of changes and modificationsbased on technological concepts of the invention to the embodiment.

[0064] For example, it is possible to adopt a display method other thanthose implemented by the embodiment whereby information is displayed interms of coordinates, as graphical representations or in terms ofnumerical values.

[0065] In addition, a location of an abnormality can also be displayedby combination of the display methods.

[0066] As described above, the present invention provides adesigned-circuit-verifying method including a process of designing apredetermined circuit; a process of simulating reference datarepresenting electrical characteristics of circuit components composingthe designed circuit; and a process of detecting electricalcharacteristics of the circuit components and comparing the detectedelectrical characteristics with the reference data.

[0067] Thus, for a circuit component of a designed circuit, electricalcharacteristics of the circuit component can be detected by simulationand compared with reference data, making it possible to identify anelectrical characteristic different from the reference data or thelocation of a circuit component having such an electrical characteristicwith ease. On the basis of a result of comparison, it is possible toshow an electrical characteristic different from the reference data on adisplay of a circuit component exhibiting the electrical characteristic.By showing such an electrical characteristic on a display of the circuitcomponent, the designed circuit can be corrected with ease. As a result,it is possible to provide a method of verifying a designed circuit toincrease a design efficiency.

[0068] While the preferred embodiment of the present invention have beendescribed using the specific terms, such description is for illustrativepurposes only, and it is to be understood that changes and variationsmay be made without departing from the spirit or scope of the followingclaims.

What is claimed is:
 1. A designed-circuit-verifying method comprising: aprocess of designing a predetermined circuit; a process of simulatingreference data representing electrical characteristics of circuitcomponents composing said designed circuit; a process of detectingelectrical characteristics of said circuit components and comparing saiddetected electrical characteristics with said reference data; a processof identifying an electrical component to be corrected on the basis of aresult of comparison so as to allow the designed circuit to be correctedwith ease.
 2. A designed-circuit-verifying method according to claim 1,further comprising: a process of displaying reference data representingan electrical characteristic of a circuit component employed in saiddesigned circuit on a computer screen if necessary; a process offetching detected data of said electrical characteristic of said circuitcomponent; a process of comparing said fetched electrical characteristicwith said reference data and forming a judgment on a result ofcomparison; and a process of displaying a result of said judgment onsaid computer screen.
 3. A designed-circuit-verifying method accordingto claim 2 wherein at least one electrical characteristic to be detectedis selected among a group of electrical characteristics including avoltage applied to a power-supply wire, a voltage drop, a powerconsumption, a current and a current direction, which are observable foreach circuit component employed in said designed circuit.
 4. Adesigned-circuit-verifying method according to claim 2 wherein at leastone electrical characteristic to be detected is selected among a groupof electrical characteristics including a current or the density of acurrent flowing through each connection hole of every circuit component,a current or the density of a current flowing through each wire, acurrent or the density of a current flowing through a multi-layer wiringsubstrate, a supplied voltage, a voltage drop and the location of eachconnection hole.